Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases. Modern consumer electronics, particularly personal portable devices, such as cellular phones, digital cameras, memory cards, MP3 players and other personal music players (PMP), require increasing functions to fit an ever-shrinking physical space.
Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cell phones, hands-free cell phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large-scale integrated circuit (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner, and the package configurations that house and protect them are required to be made smaller and thinner as well.
Many conventional semiconductor die (or “chip”) packages are of the type where a semiconductor chip is molded into a package with a resin, such as an epoxy molding compound. The packages have a leadframe with leads that are projected from the package body, to provide a path for signal transfer between the chip and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.
Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor chip onto a leadframe), a wire-bonding process (electrically connecting the semiconductor chip to leadfingers of the leadframe), a molding process (encapsulating a predetermined portion of the assembly containing the chip and leadframe with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).
The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.
An exemplary semiconductor package well known in the electronics industry is the ball-grid array (“BGA”). BGA packages typically comprise a substrate, such as a printed circuit board (“PCB”), with a semiconductor die having a multitude of bond pads mounted to the top side of the substrate. Wire bonds electrically connect the bond pads to a series of metal traces on the top side of the PCB. This series of metal traces is connected to a second series of metal traces on the backside of the PCB through a series of vias located around the outer periphery of the PCB. The second series of metal traces each terminates with a contact pad where a conductive solder ball is attached. Typically, the semiconductor die and the wire bonds are encapsulated within a molding compound.
Still thinner, smaller, and lighter package designs and mounting/connecting configurations have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding semiconductor packages that are more reliable under increasingly severe operating conditions.
In one solution, an adhesion layer was applied on the wafer level instead of to the individual chip so as to improve productivity and reduce manufacturing costs. The adhesion layer was partially cured so it could be used to attach the chip onto the leadfingers.
As the demand for semiconductor devices with increased miniaturization and greater packaging density increased, it became desirable to thin the semiconductor wafer to a thickness of less than 250 microns (approximately 10 mils). Unfortunately, having such wafer thicknesses posed a challenge to the packaging process.
Upon partially curing the adhesion layer, wafer warpage or bowing would occur because of co-efficient of thermal expansion (CTE) mismatch between the silicon of the wafer and the material of the adhesion layer. This warping would cause problems because the wafer would not lie flat for taping, dicing, and/or die attaching.
Thus, a need still remains for an integrated circuit package system with lower costs, and with higher performance, increased miniaturization, and greater packaging densities, to provide and support systems that are capable of achieving optimal thin, high-density footprint semiconductor systems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.